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TCNT—Timer Counter
7
Bit
Initial value
0
Read/Write
R/W
RSTCSR—Reset Control/Status Register
7
Bit
WRST
Initial value
0
R/(W) *
Read/Write
Watchdog timer reset
0
1
Note: * Only 0 can be written in bit 7 to clear the flag.
868
6
5
0
0
R/W
R/W
6
5
RSTOE
0
1
R/W
Reset output enable
0
External output of reset signal is disabled
1
External output of reset signal is enabled
[Clearing conditions]
• Reset signal at RES pin
• Read WRST when WRST = 1, then write 0 in WRST
[Setting condition]
TCNT overflow generates a reset signal during watchdog timer
operation
H'FFF8D (read), H'FFF8C (write)
4
3
0
0
R/W
R/W
Count value
H'FFF8F (read), H'FFF8E (write)
4
3
1
1
2
1
0
0
R/W
R/W
R/W
2
1
0
1
1
1
WDT
0
0
WDT
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