Block Diagram; Register Configuration; Figure 16.1 Ram Block Diagram; Table 16.2 System Control Register - Hitachi H8/3062 Hardware Manual

16.1.1

Block Diagram

Figure 16.1 shows a block diagram of the on-chip RAM.
Legend:
SYSCR: System control register
Note: * This example is of the H8/3062 mask ROM version operating in mode 7. The lower 20 bits
of the address are shown.
16.1.2

Register Configuration

The on-chip RAM is controlled by SYSCR. Table 16.2 gives the address and initial value of
SYSCR.

Table 16.2 System Control Register

Address *
Name
H'EE012 System control register
Note: * Lower 20 bits of the address in advanced mode
476
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
H'FEF20*
H'FEF22*
On-chip RAM
H'FFF1E*
Even addresses

Figure 16.1 RAM Block Diagram

H'FEF21*
H'FEF23*
H'FFF1F*
Odd addresses
Abbreviation R/W
SYSCR R/W
SYSCR
Initial Value
H'09