Hitachi H8/3062 Hardware Manual page 426

For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates the status of the error signal
sent back from the receiving side during transmission. Framing errors are not detected in smart
card interface mode.
Bit 4
ERS Description
Normal reception, no error signal *
0
[Clearing conditions]
•
•
1 An error signal has been sent from the receiving side indicating detection of a
parity error
[Setting condition]
The error signal is low when sampled
Note: * Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
Bit 3—Parity Error (PER): Indicates that reception of data with parity added ended abnormally
due to a parity error in asynchronous mode.
Bit 3
PER Description
Receiving is in progress or has ended normally *
0
[Clearing conditions]
•
•
A receive parity error occurred *
1
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR
Notes: *1 Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
*2 When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): The function of this bit differs for the normal serial
communication interface and for the smart card interface. Its function is switched with the SMIF
bit in SCMR.
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Indicates that when
the last bit of a serial character was transmitted TDR did not contain valid transmit data, so
transmission has ended. The TEND flag is a read-only bit and cannot be written.
378
The chip is reset or enters standby mode
Read ERS when ERS = 1, then write 0 in ERS
The chip is reset or enters standby mode
Read PER when PER = 1, then write 0 in PER
1
2
(Initial value)
(Initial value)