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FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after the start of exception handling during programming/erasing (excluding reset,
illegal instruction, trap instruction, and division-by-zero exception handling)
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a RES pin or WDT reset, or in hardware standby mode.
Notes: *1 State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled
in this state.
*2 It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify on the block being erased.
*3 FLMCR1 and EBR can be written to. However, the registers are initialized if a
transition is made to software standby mode while in the error protection state.
Figure 19.13 shows the flash memory state transition diagram.
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