Hitachi H8/3062 Hardware Manual page 904

16TCR0—Timer Control Register 0
7
Bit
—
Initial value 1
Read/Write —
Clock edge 1 and 0
Bit 4 Bit 3
CKEG CKEG0
0
0
1
Counter clear 1 and 0
Bit 6 Bit 5
CCLR1 CCLR0
0
16TCNT is not cleared
0
1
16TCNT is cleared by GRA compare match or input capture
0 16TCNT is cleared by GRB compare match or input capture
1
Synchronous clear : 16TCNT is cleared in synchronization with
1
other synchronized timers
856
6 5
CCLR1 CCLR0
0 0
R/W R/W
Timer prescaler 2 to 0
Bit 2 Bit 1 Bit 0
TPSC2 TPSC1 TPSC0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0 Rising edges counted
1
Falling edges counted
—
Both edges counted
H'FFF68
4 3
CKEG1 CKEG0 TPSC2
0 0
R/W R/W R/W
Internal clock : ø
Internal clock : ø / 2
Internal clock : ø / 4
Internal clock : ø / 8
External clock A : TCLKA input
External clock B : TCLKB input
External clock C : TCLKC input
External clock D : TCLKD input
Description
Description
16-bit timer channel 0
2 1 0
TPSC1 TPSC0
0 0 0
R/W R/W
Description
(Initial value)
(Initial value)
(Initial value)