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BCR—Bus Control Register
7
Bit
ICIS1
Initial value
1
Read/Write
R/W
Idle cycle insertion 0
0
1
Idle cycle insertion 1
0
No idle cycle is inserted in case of consecutive external read cycles for different areas
1
Idle cycle is inserted in case of consecutive external read cycles for different areas
Note: * These bits can be read and written, but must not be set to 1. Normal operation cannot be
guaranteed if 1 is written in these bits.
840
6
5
4
ICIS0
—
—
1
0*
0*
R/W
—
—
No idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle is inserted in case of consecutive external read and write cycles
H'EE024
3
2
1
—
—
RDEA
0*
1
1
—
—
R/W
Wait pin enable
0
1
Area division unit select
Area divisions are as follows:
0
Area 0: 2 MB
Area 1: 2 MB
Area 2: 8 MB
Area 3: 2 MB
1
Areas 0 to 7 are the same size
(2 MB)
Bus controller
0
WAITE
0
R/W
WAIT pin wait input is disabled
WAIT pin wait input is enabled
Area 4: 1.93 MB
Area 5: 4 kB
Area 6: 23.75 kB
Area 7: 22 B
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