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21.4.2
Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
IRQ
pin, or by input at the RES or STBY pin.
2
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
CPU.
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
21.4.3
Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 21.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
When Using an External Clock
1. H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061
mask ROM version, H8/3060 mask ROM version:
Any setting is permitted.
2. H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM
B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version,
and H8/3060 mask ROM B-mask version:
Set bits STS2 to STS0 and bits DIV0 and DIV1 to give a wait time of at least 100 µs.
, IRQ
0
, IRQ
, and IRQ
are cleared to 0, or if these interrupts are masked in the
0
1
2
, or IRQ
interrupt request signal is received, the
1
2
, IRQ
, or
0
1
643
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