Hitachi HD6433061B Manuals

Manuals and User Guides for Hitachi HD6433061B. We have 1 Hitachi HD6433061B manual available for free PDF download: Hardware Manual

Hitachi HD6433061B Hardware Manual (995 pages)

Single-Chip Microcomputer H8/3062 Series; H8/3062B Series; H8/3062F-ZTAT series; H8/3064F-ZTAT series

Brand: Hitachi | Category: Computer Hardware | Size: 4.08 MB

Table of Contents
17
Section 1 Overview

49
- Overview
  49
Tables

50
Section 2 CPU

77
- Overview
  77
  - Features
    77
  - Differences from H8/300 CPU
    78
- CPU Operating Modes
  79
- Address Space
  79
- Figure 2.1 CPU Operating Modes
  79
- Figure 2.2 Memory Map
  79
- Register Configuration
  80
  - Overview
    80
  - Figure 2.3 CPU Registers
    80
  - 2.4.2 General Registers
    81
  - Figure 2.4 Usage of General Registers
    81
  - Figure 2.5 Stack
    81
  - Table 3.2 Registers
    81
  - Control Registers
    82
  - Initial CPU Register Values
    83
- Data Formats
  84
- Instruction Set
  87
- Addressing Modes and Effective Address Calculation
  101
- Processing States
  107
  - Overview
    107
  - Program Execution State
    107
  - Figure 2.11 Processing States
    107
  - Exception-Handling State
    108
  - Figure 2.12 Classification of Exception Sources
    108
  - Table 2.14 Exception Handling Types and Priority
    108
  - Exception Handling Operation
    109
  - Figure 2.13 State Transitions
    109
  - Bus-Released State
    110
  - Reset State
    110
  - Figure 2.14 Stack Structure after Exception Handling
    110
  - Power-Down State
    111
- Basic Operational Timing
  111
Section 3 MCU Operating Modes

115
Section 4 Exception Handling

133
- Overview
  133
  - Exception Handling Types and Priority
    133
  - Exception Handling Operation
    133
  - Table 4.1 Exception Types and Priority
    133
  - Exception Vector Table
    134
  - Figure 4.1 Exception Sources
    134
  - Table 4.2 Exception Vector Table
    135
- Reset
  136
  - Overview
    136
  - Reset Sequence
    136
  - Figure 4.2 Reset Sequence (Modes 1 and 3)
    137
  - Figure 4.3 Reset Sequence (Modes 2 and 4)
    138
  - Interrupts after Reset
    139
  - Figure 4.4 Reset Sequence (Mode 6)
    139
- Interrupts
  140
- Trap Instruction
  140
- Figure 4.5 Interrupt Sources and Number of Interrupts
  140
- Stack Status after Exception Handling
  141
- Figure 4.6 Stack after Completion of Exception Handling
  141
- Notes on Stack Usage
  142
- Figure 4.7 Operation When SP Value Is Odd
  143
Section 5 Interrupt Controller

145
Section 6 Bus Controller

171
Section 7 I/O Ports

213
- Overview
  213
- Table 7.1 Port Functions
  213
- Port 1
  217
  - Overview
    217
  - Register Descriptions
    217
  - Figure 7.1 Port 1 Pin Configuration
    217
  - Table 7.2 Port 1 Registers
    217
- Port 2
  220
  - Overview
    220
  - Figure 7.2 Port 2 Pin Configuration
    220
  - Register Descriptions
    221
  - Table 7.3 Port 2 Registers
    221
  - Table 7.4 Input Pull-Up Transistor States (Port 2)
    223
- Port 3
  224
  - Overview
    224
  - Register Descriptions
    224
  - Figure 7.3 Port 3 Pin Configuration
    224
  - Table 7.5 Port 3 Registers
    224
- Port 4
  226
  - Overview
    226
  - Figure 7.4 Port 4 Pin Configuration
    226
  - Register Descriptions
    227
  - Table 7.6 Port 4 Registers
    227
- Port 5
  229
  - Overview
    229
  - Figure 7.5 Port 5 Pin Configuration
    229
  - Table 7.7 Input Pull-Up Transistor States (Port 4)
    229
  - Register Descriptions
    230
  - Table 7.8 Port 5 Registers
    230
- Port 6
  232
  - Overview
    232
  - Table 7.9 Input Pull-Up Transistor States (Port 5)
    232
  - Register Descriptions
    233
  - Figure 7.6 Port 6 Pin Configuration
    233
  - Table 7.10 Port 6 Registers
    233
  - Table 7.11 Port 6 Pin Functions in Modes 1 to 5
    235
- Port 7
  236
  - Overview
    236
  - Figure 7.7 Port 7 Pin Configuration
    236
  - Register Description
    237
  - Table 7.12 Port 7 Data Register
    237
- Port 8
  238
  - Overview
    238
  - Figure 7.8 Port 8 Pin Configuration
    238
  - Register Descriptions
    239
  - Table 7.13 Port 8 Registers
    239
  - Table 7.14 Port 8 Pin Functions in Modes 1 to 5
    241
  - Table 7.15 Port 8 Pin Functions in Modes 6 and 7
    242
- Port 9
  243
  - Overview
    243
  - Figure 7.9 Port 9 Pin Configuration
    243
  - Register Descriptions
    244
  - Table 7.16 Port 9 Registers
    244
  - Table 7.17 Port 9 Pin Functions
    246
- Port a
  248
- Port B
  260
  - Overview
    260
  - Figure 7.11 Port B Pin Configuration
    261
  - Register Descriptions
    262
  - Table 7.22 Port B Registers
    262
  - Table 7.23 Port B Pin Functions (Modes 1 to 5)
    264
  - Table 7.24 Port B Pin Functions (Modes 6 and 7)
    266
Section 8 16-Bit Timer

269
8-Bit Timers

333
Section 10 Programmable Timing Pattern Controller (TPC)

371
- Overview
  371
  - Features
    371
  - Block Diagram
    372
  - Figure 10.1 TPC Block Diagram
    372
  - Pin Configuration
    373
  - Table 10.1 TPC Pins
    373
  - Register Configuration
    374
  - Table 10.2 TPC Registers
    374
- Register Descriptions
  375
  - Port a Data Direction Register (PADDR)
    375
  - Port a Data Register (PADR)
    375
  - Port B Data Direction Register (PBDDR)
    376
  - Port B Data Register (PBDR)
    376
  - Next Data Register a (NDRA)
    377
  - Next Data Register B (NDRB)
    379
  - Next Data Enable Register a (NDERA)
    381
  - Next Data Enable Register B (NDERB)
    382
  - TPC Output Control Register (TPCR)
    383
  - TPC Output Mode Register (TPMR)
    385
- Operation
  387
- Usage Notes
  394
Section 11 Watchdog Timer

397
- Overview
  397
  - Features
    397
  - Block Diagram
    398
  - Pin Configuration
    398
  - Figure 11.1 WDT Block Diagram
    398
  - Table 11.1 WDT Pin
    398
  - Register Configuration
    399
- Register Descriptions
  399
- Operation
  405
- Interrupts
  408
- Usage Notes
  408
- Figure 11.8 Contention between TCNT Write and Count up
  408
Section 12 Serial Communication Interface

409
Section 13 Smart Card Interface

469
Section 14 A/D Converter

495
Section 15 D/A Converter

515
- Overview
  515
  - Features
    515
  - Block Diagram
    516
  - Figure 15.1 D/A Converter Block Diagram
    516
  - Pin Configuration
    517
  - Register Configuration
    517
  - Table 15.1 D/A Converter Pins
    517
  - Table 15.2 D/A Converter Registers
    517
- Register Descriptions
  518
- Operation
  520
- Figure 15.2 Example of D/A Converter Operation
  521
- D/A Output Control
  522
Section 16 RAM

523
- Overview
  523
  - Table 16.1 H8/3062 Series On-Chip RAM Specifications
    523
  - Block Diagram
    524
  - Figure 16.1 RAM Block Diagram
    524
  - Register Configuration
    524
  - Table 16.2 System Control Register
    524
- System Control Register (SYSCR)
  525
- Operation
  526
Section 17 ROM

527
Section 18 H8/3064 Internal Voltage Step-Down Version ROM

571
[H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions

623
- Table 19.1 Operating Modes and ROM
  623
Of H8/3062, H8/3061, and H8/3060]

623
Section 20 Clock Pulse Generator

675
Section 21 Power-Down State

683
Section 22 Electrical Characteristics

699
Appendix A Instruction Set

811
- Instruction List
  811
  - Table A.1 Instruction Set
    813
  - Arithmetic Instructions
    815
  - Bit Manipulation Instructions
    820
- Operation Code Maps
  826
- Number of States Required for Execution
  829
  - Table A.3 Number of States Per Cycle
    830
  - Table A.4 Number of Cycles Per Instruction
    831
Appendix B Internal I/O Registers

838
Appendix C I/O Port Block Diagrams

944
Appendix D Pin States

974
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

981
Appendix F Product Code Lineup

982
- Table F.1 H8/3062 Series
  982
Appendix G Package Dimensions

984
- Figure G.1 Package Dimensions (FP-100B)
  984
- H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)
  990

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Hitachi HD6433061B Manuals

Hitachi HD6433061B Hardware Manual (995 pages)

Table of Contents

Section 1 Overview

Tables

Figures

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 I/O Ports

Section 8 16-Bit Timer

8-Bit Timers

Section 10 Programmable Timing Pattern Controller (TPC)

Section 11 Watchdog Timer

Section 12 Serial Communication Interface

Section 13 Smart Card Interface

Section 14 A/D Converter

Section 15 D/A Converter

Section 16 RAM

Section 17 ROM

Section 18 H8/3064 Internal Voltage Step-Down Version ROM

[H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions

Of H8/3062, H8/3061, and H8/3060]

Section 20 Clock Pulse Generator

Section 21 Power-Down State

Section 22 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Registers

Appendix C I/O Port Block Diagrams

Appendix D Pin States

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Appendix F Product Code Lineup

Appendix G Package Dimensions

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