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Type
Symbol
Data bus
D
to D
15
0
CS
Bus
to
7
CS
control
0
AS
RD
HWR
LWR
WAIT
16-bit
TCLKD to
timer
TCLKA
TIOCA
to
2
TIOCA
0
TIOCB
to
2
TIOCB
0
8-bit timer TMO
,
0
TMO
2
TMIO
,
1
TMIO
3
TCLKD to
TCLKA
Program-
TP
to
15
mable
TP
0
timing
pattern
controller
(TPC)
Pin No.
FP-100B
TFP-100B FP-100A I/O
34 to 23,
36 to 25,
21 to 18
23 to 20
2 to 5,
4 to 7,
88 to 91
90 to 93
69
71
70
72
71
73
72
74
58
60
96 to 93
98 to95
99, 97, 95 1, 99, 97 Input/
100, 98,
2, 100,
96
98
2, 4
4, 6
3, 5
5, 7
96 to 93
98 to 95 Input
9 to 2,
11 to 4,
100 to 93
2, 1,
100 to
95
Name and Function
Input/
Data bus: Bidirectional data bus
output
Output Chip select: Select signals for areas 7 to 0.
Output Address strobe: Goes low to indicate valid
address output on the address bus.
Output Read: Goes low to indicate reading from the
external address space.
Output High write: Goes low to indicate writing to the
external address space; indicates valid data
on the upper data bus (D
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data
on the lower data bus (D
Input
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space.
Input
Clock input D to A: External clock inputs
Input capture/output compare A2 to A0:
output
GRA2 to GRA0 output compare or input
capture, or PWM output
Input/
Input capture/output compare B2 to B0:
output
GRB2 to GRB0 output compare or input
capture
Output Compare match output: Compare match
output pins
Input/
Input capture input/compare match output:
output
Input capture input or compare match output
pins
Counter external clock input: These pins
input an external clock to the counters.
Output TPC output 15 to 0: Pulse output
to D
).
15
8
to D
).
7
0
15
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