Ram Control Register (Ramcr); Table 17.4 Flash Memory Erase Blocks - Hitachi H8/3062 Hardware Manual

Table 17.4 Flash Memory Erase Blocks

Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (32 kbytes)
EB6 (32 kbytes)
EB7 (32 kbytes)
17.3.3

RAM Control Register (RAMCR)

RAMCR selects the RAM area to be used when emulating real-time flash memory programming.
Bit
Modes 1 Initial value
to 4
Read/Write
Modes 5
Initial value
to 7
Read/Write
Note: * Cannot be set to 1 in mode 6.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—RAM Select (RAMS): Used with bits 2 to 1 to reassign an area to RAM (see table 17.5).
The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled * . In modes other than 5 to 7, 0 is always read and writing is disabled.
This bit is initialized by a reset and in hardware standby mode. It is not initialized in software
standby mode.
When bit 3 is set, all flash-memory blocks are protected from programming and erasing.
Address
H'000000–H'0003FF
H'000400–H'0007FF
H'000800–H'000BFF
H'000C00–H'000FFF
H'001000–H'007FFF
H'008000–H'00FFFF
H'010000–H'017FFF
H'018000–H'01FFFF
7 6 5
— — —
1 1 1
— — —
1 1 1
— — —
Reserved bits
4 3 2
— RAMS RAM2
1 0 0
— R R
1 0 0
R/W * R/W *
—
RAM2, RAM1
Used together with bit 3 to select
a flash memory area
RAM select
Used together with bits 2 and 1 to select
a flash memory area
1 0
RAM1 —
0 1
R —
0 1
R/W *
—
Reserved bit
487