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9.2
Register Descriptions
9.2.1
Timer Counters (8TCNT)
Bit
15
14
Initial value
0
0
Read/Write
R/W
R/W
Bit
15
14
Initial value
0
0
Read/Write
R/W
R/W
The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses
generated from an internal or external clock source. The clock source is selected by clock select
bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or
write to the timer counters.
The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a
16-bit register by word access.
8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1
and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing.
When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status
register (8TCSR) is set to 1.
Each 8TCNT is initialized to H'00 by a reset and in standby mode.
290
8TCNT0
13
12
11
10
0
0
0
0
R/W
R/W
R/W
R/W
8TCNT2
13
12
11
10
0
0
0
0
R/W
R/W
R/W
R/W
9
8
7
6
0
0
0
0
R/W
R/W
R/W
R/W
9
8
7
6
0
0
0
0
R/W
R/W
R/W
R/W
8TCNT1
5
4
3
2
0
0
0
0
R/W
R/W
R/W
R/W
8TCNT3
5
4
3
2
0
0
0
0
R/W
R/W
R/W
R/W
1
0
0
0
R/W
R/W
1
0
0
0
R/W
R/W
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