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mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the
corresponding pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Bit
PA
Initial value
Read/Write
R/W
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7
6
5
PA
PA
7
6
0
0
0
R/W
R/W
4
3
PA
PA
5
4
3
0
0
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
2
1
PA
PA
PA
2
1
0
0
R/W
R/W
R/W
0
0
0
203
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