Hitachi H8/3062 Hardware Manual page 35

Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access).................................................................................................... 152
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address) .......................................................................... 153
Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address) ........................................................................... 154
Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access).................................................................................................... 155
Figure 6.17 Example of Wait State Insertion Timing............................................................ 156
Figure 6.18 Example of Idle Cycle Operation (ICIS1 = 1).................................................... 157
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1).................................................... 158
Figure 6.20 Example of Idle Cycle Operation ....................................................................... 158
Figure 6.21 Example of External Bus Master Operation ...................................................... 161
Figure 6.22 ASTCR Write Timing ........................................................................................ 162
Figure 6.23 DDR Write Timing............................................................................................. 162
Figure 6.24 BRCR Write Timing .......................................................................................... 163
Figure 7.1 Port 1 Pin Configuration .................................................................................... 169
Figure 7.2 Port 2 Pin Configuration .................................................................................... 172
Figure 7.3 Port 3 Pin Configuration .................................................................................... 176
Figure 7.4 Port 4 Pin Configuration .................................................................................... 178
Figure 7.5 Port 5 Pin Configuration .................................................................................... 181
Figure 7.6 Port 6 Pin Configuration .................................................................................... 185
Figure 7.7 Port 7 Pin Configuration .................................................................................... 188
Figure 7.8 Port 8 Pin Configuration .................................................................................... 190
Figure 7.9 Port 9 Pin Configuration .................................................................................... 195
Figure 7.10 Port A Pin Configuration.................................................................................... 201
Figure 7.11 Port B Pin Configuration.................................................................................... 213
Figure 8.1 16-bit timer Block Diagram (Overall)................................................................ 223
Figure 8.2 Block Diagram of Channels 0 and 1 .................................................................. 224
Figure 8.3 Block Diagram of Channel 2.............................................................................. 225
16TCNT Access Operation [CPU → 16TCNT (Word)].................................... 248
Figure 8.4
Figure 8.5 Access to Timer Counter (CPU Reads 16TCNT, Word) ................................... 248
Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte).............. 249
Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) .............. 249
Figure 8.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte) ................... 249
Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) ................... 250
Figure 8.10 16TCR Access (CPU Writes to 16TCR)............................................................ 250
Figure 8.11 16TCR Access (CPU Reads 16TCR) ................................................................. 250
Figure 8.12 Counter Setup Procedure (Example).................................................................. 252
Figure 8.13 Free-Running Counter Operation ....................................................................... 253
Figure 8.14 Periodic Counter Operation................................................................................ 253
Figure 8.15 Count Timing for Internal Clock Sources .......................................................... 254
Figure 8.16 Count Timing for External Clock Sources (when Both Edges are Detected) .... 254
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