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9.2.5
Timer Control/Status Registers (8TCSR)
8TCSR0
Bit
CMFB
Initial value
Read/Write
R/(W)*
8TCSR2
Bit
CMFB
Initial value
Read/Write
R/(W)*
8TCSR1, 8TCSR3
Bit
CMFB
Initial value
Read/Write
R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input
capture and overflow statuses, and control compare match output/input capture edge selection.
8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in
standby mode.
292
7
6
CMFA
OVF
0
0
R/(W)*
R/(W)*
7
6
CMFA
OVF
0
0
R/(W)*
R/(W)*
7
6
CMFA
OVF
0
0
R/(W)*
R/(W)*
5
4
OIS3
ADTE
0
0
R/W
R/W
5
4
—
OIS3
0
1
—
R/W
5
4
ICE
OIS3
0
0
R/W
R/W
3
2
OIS2
OS1
0
0
R/W
R/W
3
2
OIS2
OS1
0
0
R/W
R/W
3
2
OIS2
OS1
0
0
R/W
R/W
1
0
OS0
0
0
R/W
1
0
OS0
0
0
R/W
1
0
OS0
0
0
R/W
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