Table of Contents
Advertisement
16.2
System Control Register (SYSCR)
Bit
SSBY
Initial value
Read/Write
R/W
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
7
6
STS2
STS1
0
0
R/W
R/W
Standby timer select 2 to 0
5
4
STS0
UE
0
0
R/W
R/W
User bit enable
3
2
NMIEG
SSOE
1
0
R/W
R/W
Software standby
output port enable
NMI edge select
1
0
RAME
0
1
R/W
RAM enable bit
Enables or
disables
on-chip RAM
(Initial value)
473
Advertisement
Table of Contents
