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10.1.4
Register Configuration
Table 10.2 summarizes the TPC registers.
Table 10.2 TPC Registers
1
Address*
Name
H'EE009
Port A data direction register
H'FFFD9
Port A data register
H'EE00A
Port B data direction register
H'FFFDA
Port B data register
H'FFFA0
TPC output mode register
H'FFFA1
TPC output control register
H'FFFA2
Next data enable register B
H'FFFA3
Next data enable register A
H'FFFA5/
Next data register A
3
H'FFFA7*
H'FFFA4/
Next data register B
3
H'FFFA6*
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC
output groups 0 and 1 by settings in TPCR. When the output triggers are different, the
NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address
of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2
and 3 by settings in TPCR. When the output triggers are different, the NDRB address is
H'FFFA6 for group 2 and H'FFFA4 for group 3.
322
Abbreviation
R/W
PADDR
W
PADR
R/(W)*
PBDDR
W
PBDR
R/(W)*
TPMR
R/W
TPCR
R/W
NDERB
R/W
NDERA
R/W
NDRA
R/W
NDRB
R/W
Initial Value
H'00
2
H'00
H'00
2
H'00
H'F0
H'FF
H'00
H'00
H'00
H'00
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