Register Configuration - Hitachi H8/3062 Hardware Manual

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9.1.4

Register Configuration

Table 9.2 summarizes the registers of the 8-bit timer module.
Table 9.2
8-Bit Timer Registers
Channel Address*1
0
H'FFF80
H'FFF82
H'FFF84
H'FFF86
H'FFF88
1
H'FFF81
H'FFF83
H'FFF85
H'FFF87
H'FFF89
2
H'FFF90
H'FFF92
H'FFF94
H'FFF96
H'FFF98
3
H'FFF91
H'FFF93
H'FFF95
H'FFF97
H'FFF99
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0
register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed
together by word access.
Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the
channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be
accessed together by word access.
Name
Timer control register 0
Timer control/status register 0
Time constant register A0
Time constant register B0
Timer counter 0
Timer control register 1
Timer control/status register 1
Time constant register A1
Time constant register B1
Timer counter 1
Timer control register 2
Timer control/status register 2
Time constant register A2
Time constant register B2
Timer counter 2
Timer control register 3
Timer control/status register 3
Time constant register A3
Time constant register B3
Timer counter 3
Abbreviation R/W
8TCR0
R/W
8TCSR0
R/(W)*
TCORA0
R/W
TCORB0
R/W
8TCNT0
R/W
8TCR1
R/W
8TCSR1
R/(W)*
TCORA1
R/W
TCORB1
R/W
8TCNT1
R/W
8TCR2
R/W
8TCSR2
R/(W)*
TCORA2
R/W
TCORB2
R/W
8TCNT2
R/W
8TCR3
R/W
8TCSR3
R/(W)*
TCORA3
R/W
TCORB3
R/W
8TCNT3
R/W
Initial value
H'00
2
H'00
H'FF
H'FF
H'00
H'00
2
H'00
H'FF
H'FF
H'00
H'00
2
H'10
H'FF
H'FF
H'00
H'00
2
H'00
H'FF
H'FF
H'00
285

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