Hitachi H8/3062 Hardware Manual page 639

Table 20.3 (1) Clock Timing for On-Chip Flash Memory Versions
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
includes a RES pulse width (t
Note: * t
DEXT
Table 20.3 (2) Clock Timing for On-Chip Mask ROM Versions
Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise
time
External clock fall
time
Clock low pulse
width
Clock high pulse
width
External clock output
settling delay time
includes the RES pulse width (t
Note: * t
DEXT
V = 3.0 V
CC
to 5.5 V
Symbol Min
t 30
EXL
t 30
EXH
t —
EXr
t —
EXf
t 0.4
CL
80
t 0.4
CH
80
t * 500
DEXT
V = 2.7 V
CC
to 5.5 V
Symbol Min Max
t 40 —
EXL
t 40 —
EXH
t — 10
EXr
t — 10
EXf
t 0.4 0.6
CL
80 —
t 0.4 0.6
CH
80 —
t * 500 —
DEXT
V = 5.0 V
CC
± 10%
Max Min
— 15
— 15
8 —
8 —
0.6 0.4
— 80
0.6 0.4
— 80
— 500
). t = 20 t
RESW RESW cyc
V = 3.0 V V
CC
to 5.5 V ± 10%
Min Max Min
30 — 15
30 — 15
— 8 —
— 8 —
0.4 0.6 0.4
80 — 80
0.4 0.6 0.4
80 — 80
500 — 500
). t = 10 t
RESW RESW cyc
Max Unit Test Conditions
— ns Figure 20.6
— ns
5 ns
5 ns
φ ≥ 5 MHz Figure
0.6 t
cyc
φ < 5 MHz
— ns
φ ≥ 5 MHz
0.6 t
cyc
φ < 5 MHz
— ns
— µs Figure 20.7
= 5.0 V
CC
Max Unit Test Conditions
— ns Figure 20.6
— ns
5 ns
5 ns
φ ≥ 5 MHz Figure
0.6 t
cyc
φ < 5 MHz
— ns
φ ≥ 5 MHz
0.6 t
cyc
φ < 5 MHz
— ns
— µs Figure 20.7
.
22.17
22.17
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