Hitachi H8/3062 Hardware Manual page 19

13.3.2 Pin Connections .................................................................................................... 425
13.3.3 Data Format........................................................................................................... 426
13.3.4 Register Settings.................................................................................................... 428
13.3.5 Clock ..................................................................................................................... 430
13.3.6 Transmitting and Receiving Data.......................................................................... 432
13.4 Usage Notes........................................................................................................................ 439
Section 14 A/D Converter
14.1 Overview ............................................................................................................................ 443
14.1.1 Features ................................................................................................................. 443
14.1.2 Block Diagram ...................................................................................................... 444
14.1.3 Pin Configuration .................................................................................................. 445
14.1.4 Register Configuration .......................................................................................... 446
14.2 Register Descriptions.......................................................................................................... 446
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 446
14.2.2 A/D Control/Status Register (ADCSR) ................................................................ 447
14.2.3 A/D Control Register (ADCR).............................................................................. 449
14.3 CPU Interface ..................................................................................................................... 450
14.4 Operation ............................................................................................................................ 452
14.4.1 Single Mode (SCAN = 0)...................................................................................... 452
14.4.2 Scan Mode (SCAN = 1) ........................................................................................ 454
14.4.3 Input Sampling and A/D Conversion Time .......................................................... 456
14.4.4 External Trigger Input Timing .............................................................................. 457
14.5 Interrupts ............................................................................................................................ 458
14.6 Usage Notes........................................................................................................................ 458
Section 15 D/A Converter
15.1 Overview ............................................................................................................................ 463
15.1.1 Features ................................................................................................................. 463
15.1.2 Block Diagram ...................................................................................................... 464
15.1.3 Pin Configuration .................................................................................................. 465
15.1.4 Register Configuration .......................................................................................... 465
15.2 Register Descriptions.......................................................................................................... 466
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 466
15.2.2 D/A Control Register (DACR).............................................................................. 466
15.2.3 D/A Standby Control Register (DASTCR) ........................................................... 468
15.3 Operation ............................................................................................................................ 468
15.4 D/A Output Control............................................................................................................ 470
Section 16 RAM
16.1 Overview ............................................................................................................................ 471
16.1.1 Block Diagram ...................................................................................................... 472
16.1.2 Register Configuration .......................................................................................... 472
.................................................................................................. 443
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