Hitachi H8/3062 Hardware Manual page 250

Bit 5
IMIEA1 Description
0 IMIA1 interrupt requested by IMFA1 flag is disabled
1 IMIA1 interrupt requested by IMFA1 flag is enabled
Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables
the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4
IMIEA0 Description
0 IMIA0 interrupt requested by IMFA0 flag is disabled
1 IMIA0 interrupt requested by IMFA0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2
compare match or input capture events.
Bit 2
IMFA2 Description
0 [Clearing condition]
Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag
1 [Setting conditions]
•
16TCNT2 = GRA2 when GRA2 functions as an output compare register
•
16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register
Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1
compare match or input capture events.
Bit 1
IMFA1 Description
0 [Clearing condition]
Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag
1 [Setting conditions]
•
16TCNT1 = GRA1 when GRA1 functions as an output compare register
•
16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1
functions as an input capture register
230
(Initial value)
(Initial value)
(Initial value)
(Initial value)