Flash Memory Protection; Hardware Protection - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer

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Flash Memory Protection

There are three kinds of flash memory program/erase protection: hardware, software, and error

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and

erase block register (EBR) are reset. In the error protection state, the FLMCR1 and EBR settings

are retained; the P bit and E bit can be set, but a transition is not made to program mode or erase

mode. (See table 19.9.)

Table 19.9 Hardware Protection

When a low level is input to the FWE pin,

FLMCR1 and EBR are initialized, and the

program/erase-protected state is entered.

In a reset (including a WDT overflow reset)

and in standby mode, FLMCR1 and EBR are

initialized, and the program/erase-protected

state is entered.

In a reset via the RES pin, the reset state is not

entered unless the RES pin is held low until

oscillation stabilizes after powering on. In the

case of a reset during operation, hold the RES

pin low for the RES pulse width specified in the

AC Characteristics section.*

When a microcomputer operation error (error

generation (FLER = 1)) was detected while flash

memory was being programmed/erased, error

protection is enabled. At this time, the FLMCR1

and EBR settings are held, but

programming/erasing is aborted at the time the

error was generated. Error protection is released

only by a reset via the RES pin or a WDT reset,

or in the hardware standby mode.

Notes: 1. The RAM area that overlapped flash memory is deleted.

2. It is possible to perform a program-verify operation on the 128 bytes being

programmed, or an erase-verify operation on the block being erased.

Program Erase