Table of Contents
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6.2.5
Bus Control Register (BCR) ................................................................................. 131
6.2.6
Chip Select Control Register (CSCR)................................................................... 133
6.2.7
Address Control Register (ADRCR)..................................................................... 134
6.3
Operation ............................................................................................................................ 135
6.3.1
Area Division ........................................................................................................ 135
6.3.2
Bus Specifications ................................................................................................. 138
6.3.3
Memory Interfaces ................................................................................................ 139
6.3.4
Chip Select Signals................................................................................................ 139
6.3.5
Address Output Method ........................................................................................ 140
6.4
Basic Bus Interface............................................................................................................. 142
6.4.1
Overview ............................................................................................................... 142
6.4.2
Data Size and Data Alignment.............................................................................. 142
6.4.3
Valid Strobes ......................................................................................................... 143
6.4.4
Memory Areas....................................................................................................... 144
6.4.5
Basic Bus Control Signal Timing.......................................................................... 145
6.4.6
Wait Control.......................................................................................................... 152
6.5
Idle Cycle............................................................................................................................ 154
6.5.1
Operation ............................................................................................................... 154
6.5.2
Pin States in Idle Cycle ......................................................................................... 156
6.6
Bus Arbiter ......................................................................................................................... 156
6.6.1
Operation ............................................................................................................... 157
6.7
Register and Pin Input Timing ........................................................................................... 159
6.7.1
Register Write Timing .......................................................................................... 159
BREQ Pin Input Timing........................................................................................ 160
6.7.2
Section 7
7.1
Overview ............................................................................................................................ 161
7.2
Port 1 .................................................................................................................................. 165
7.2.1
Overview ............................................................................................................... 165
7.2.2
Register Descriptions ............................................................................................ 165
7.3
Port 2 .................................................................................................................................. 168
7.3.1
Overview ............................................................................................................... 168
7.3.2
Register Descriptions ............................................................................................ 169
7.4
Port 3 .................................................................................................................................. 172
7.4.1
Overview ............................................................................................................... 172
7.4.2
Register Descriptions ............................................................................................ 172
7.5
Port 4 .................................................................................................................................. 174
7.5.1
Overview ............................................................................................................... 174
7.5.2
Register Descriptions ............................................................................................ 175
7.6
Port 5 .................................................................................................................................. 177
7.6.1
Overview ............................................................................................................... 177
7.6.2
Register Descriptions ............................................................................................ 178
7.7
Port 6 .................................................................................................................................. 180
iv
............................................................................................................. 161
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