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In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 5 is functioning as an input/output port and
a P5DDR bit is set to 1, the corresponding pin maintains its output state.
Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores output data
for port 5. When port 5 functions as an output port, the value of this register is output. When a bit
in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned. When a
bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin logic level is read.
Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.
Bit
Initial value
Read/Write
P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 5.
Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
—
Initial value
1
Read/Write
—
In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit in P5PCR is set to 1, the input pull-up transistor is turned on.
7
6
—
—
1
1
—
—
Reserved bits
6
5
—
—
1
1
—
—
Reserved bits
5
4
—
—
P5
1
1
—
—
R/W
4
3
—
P5 PCR
3
1
0
—
R/W
Port 5 input pull-up MOS control 3 to 0
These bits control input pull-up
transistors built into port 5
3
2
P5
P5
3
2
0
0
R/W
R/W
Port 5 data 3 to 0
These bits store data
for port 5 pins
2
1
P5 PCR
P5 PCR
2
1
0
0
R/W
R/W
1
0
P5
1
0
0
0
R/W
0
P5 PCR
0
0
R/W
179
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