Hitachi H8/3062 Hardware Manual page 675

Single-chip microcomputer
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Item
Write data delay
time
Write data setup
time 1
Write data setup
time 2
Write data hold
time
Read data access
time 1
Read data access
time 2
Read data access
time 3
Read data access
time 4
Precharge time 1
Precharge time 2
Wait setup time
Wait hold time
Bus request setup
time
Bus acknowledge
delay time 1
Bus acknowledge
delay time 2
Bus-floating time
Note: In order to secure the address hold time relative to the rise of the RD strobe, address
update mode 2 should be used. For details see section 6.3.5, Address Output Method.
660
A
Symbol
Min
Max
t
60
WDD
t
1.0 t
WDS1
cyc
– 50
t
2.0 t
WDS2
cyc
– 50
t
0.5 t
WDH
cyc
– 30
t
2.0 t
ACC1
– 100
t
3.0 t
ACC2
– 100
t
1.5 t
ACC3
– 100
t
2.5 t
ACC4
– 100
t
1.0 t
PCH1
cyc
– 40
t
0.5 t
PCH2
cyc
– 40
t
40
WTS
t
5
WTH
t
40
BRQS
t
60
BACD1
t
60
BACD2
t
60
BZD
Condition
B
Min
Max
50
1.0 t
cyc
– 40
2.0 t
cyc
– 40
0.5 t
cyc
– 25
2.0 t
cyc
cyc
– 80
3.0 t
cyc
cyc
– 80
1.5 t
cyc
cyc
– 80
2.5 t
cyc
cyc
– 80
1.0 t
cyc
– 30
0.5 t
cyc
– 30
40
5
40
50
50
50
C
Min
Max
Unit Conditions
35
ns
1.0 t
ns
cyc
– 30
2.0 t
ns
cyc
– 30
0.5 t
ns
cyc
– 15
2.0 t
ns
cyc
– 45
3.0 t
ns
cyc
– 45
1.5 t
ns
cyc
– 45
2.5 t
ns
cyc
– 45
1.0 t
ns
cyc
– 20
0.5 t
ns
cyc
– 20
25
ns
5
ns
25
ns
30
ns
30
ns
30
ns
Test
Figure 22.17,
figure 22.18
Figure 22.19
Figure 22.20

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