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Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms. See table 21.3. If an external
clock is used, the choice of settings depends on the H8/3062 Series version.
1. H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061
mask ROM version, H8/3060 mask ROM version:
Any setting is permitted.
2. H8/3064F-ZTAT, H8/3062F-ZTAT A-mask version:
Choose a setting, according to the operating frequency, that gives a wait time of at least
100 µs.
Bit 6
Bit 5
STS2
STS1
0
0
1
1
0
1
0
1
1
1
1
630
Bit 4
STS0
Description
0
Waiting time = 8,192 states
1
Waiting time = 16,384 states
0
Waiting time = 32,768 states
1
Waiting time = 65,536 states
0
Waiting time = 131,072 states
1
Waiting time = 262,144 states
0
Waiting time = 1,024 states
1
Illegal setting
(Initial value)
(Initial value)
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