Hitachi H8/3062 Hardware Manual page 803

Data
Address Register Bus
(Low) Name Width Bit 7
H'FFFD3 P4DR 8
H'FFFD4 P5DR 8
H'FFFD5 P6DR 8
H'FFFD6 P7DR 8
H'FFFD7 P8DR 8
H'FFFD8 P9DR 8
H'FFFD9 PADR 8
H'FFFDA PBDR 8
H'FFFDB —
H'FFFDC —
H'FFFDD —
H'FFFDE —
H'FFFDF —
H'FFFE0 ADDRAH 8
H'FFFE1 ADDRAL 8
H'FFFE2 ADDRBH 8
H'FFFE3 ADDRBL 8
H'FFFE4 ADDRCH 8
H'FFFE5 ADDRCL 8
H'FFFE6 ADDRDH 8
H'FFFE7 ADDRDL 8
H'FFFE8 ADCSR 8
H'FFFE9 ADCR 8
Notes: 1. Writing to bits 6 to 0 of FLMCR2 is prohibited.
2. Writing to bits 5 to 3 of BCR is prohibited.
3. For the procedure for writing to TCSR, TCNT, and RSTCSR, see section 11.2.4, Notes
on Register Rewriting.
4. The address depends on the output trigger setting.
5. Use byte access on FLMCR1, FLMCR2, EBR1, EBR2, and RAMCR.
Legend:
WDT: Watchdog timer
TPC: Programmable timing pattern controller
SCI: Serial communication interface
788
Bit 6 Bit 5
P4 P4 P4
7 6 5
— — —
P6 P6 P6
7 6 5
P7 P7 P7
7 6 5
— — —
— — P9
5
PA PA PA
7 6 5
PB PB PB
7 6 5
— — —
— — —
— — —
— — —
— — —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
ADF ADIE ADST
TRGE — —
Bit Names
Bit 4 Bit 3 Bit 2
P4 P4 P4
4 3 2
— P5 P5
3 2
P6 P6 P6
4 3 2
P7 P7 P7
4 3 2
P8 P8 P8
4 3 2
P9 P9 P9
4 3 2
PA PA PA
4 3 2
PB PB PB
4 3 2
— — —
— — —
— — —
— — —
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
SCAN CKS CH2
— — —
Bit 1 Bit 0 Module Name
P4 P4 Port 4
1 0
P5 P5 Port 5
1 0
P6 P6 Port 6
1 0
P7 P7 Port 7
1 0
P8 P8 Port 8
1 0
P9 P9 Port 9
1 0
PA PA Port A
1 0
PB PB Port B
1 0
— —
— —
— —
— —
— —
AD3 AD2 A/D converter
— —
AD3 AD2
— —
AD3 AD2
— —
AD3 AD2
— —
CH1 CH0
— —