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Some functions differ between channel 0 and channel 1.
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.
9.2.5
Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
TCSR0
Bit
:
CMFB
Initial value :
R/W
:
R/(W)*
TCSR1
Bit
:
CMFB
Initial value :
R/W
:
R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and
control compare match output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.
Description
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
For channel 0: count at TCNT1 overflow signal*
For channel 1: count at TCNT0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
7
6
CMFA
OVF
0
0
R/(W)*
R/(W)*
7
6
CMFA
OVF
0
0
R/(W)*
R/(W)*
5
4
ADTE
OS3
0
0
R/W
R/W
5
4
—
OS3
0
1
—
R/W
3
2
OS2
OS1
0
0
R/W
R/W
3
2
OS2
OS1
0
0
R/W
R/W
(Initial value)
1
0
OS0
0
0
R/W
1
0
OS0
0
0
R/W
353
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