Table of Contents
Advertisement
6.3.3
Memory Interfaces
As its memory interface, the H8/3062 Series has only a basic bus interface that allows direct
connection of ROM, SRAM, and so on. It is not possible to select a DRAM interface that allows
direct connection of DRAM, or a burst ROM interface that allows direct connection of burst
ROM.
6.3.4
Chip Select Signals
For each of areas 0 to 7, the H8/3062 Series can output a chip select signal (CS
low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output
timing of a CSn signal.
Output of CS
to CS
0
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
to CS
in the input state. To output chip select signals CS
1
3
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS
to CS
in the input state. To output chip select signals CS
0
3
bits must be set to 1. For details, see section 7, I/O Ports.
Output of CS
to CS
4
register (CSCR). A reset leaves pins CS
CS
to CS
, the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports.
4
7
Address bus
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS
high. The CS
signals are decoded from the address signals. They can be used as chip select
n
signals for SRAM and other devices.
: Output of CS
to CS
3
0
: Output of CS
to CS
7
4
4
φ
CS
n
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
is enabled or disabled in the data direction register
3
is enabled or disabled in the chip select control
7
to CS
in the input state. To output chip select signals
7
External address in area n
to CS
0
in the output state and
0
to CS
, the corresponding
1
3
to CS
, the corresponding DDR
0
3
) that goes
7
to CS
remain
0
7
139
Advertisement
Table of Contents
