Table of Contents
Advertisement
16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for
a 16-bit, two-state-access area. In these areas, the upper data bus (D
even addresses and the lower data bus (D
be inserted.
Read access
Write access
Note: n = 7 to 0
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
150
to D
7
φ
Address bus
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
(Byte Access to Even Address)
) in accesses to odd addresses. Wait states cannot
0
Bus cycle
T
1
Even external address in area n
High
Valid
Undetermined data
to D
) is used in accesses to
15
8
T
2
Valid
Invalid
Advertisement
Table of Contents
