Hitachi H8/3062 Hardware Manual page 843

TSNC—Timer Synchro Register
Bit
Initial value
Read/Write
Timer sync 2
0
1
828
7 6 5
— — —
1 1 1
— — —
Reserved bits
Timer sync 0
0
1
Timer sync 1
0 Channel 1 timer counter (16TCNT1) operates
independently (16TCNT1 presetting/clearing is
independent of other channels)
1 Channel 1 operates synchronously
Synchronous presetting/synchronous clearing
of 16TCNT1 is possible
Channel 2 timer counter (16TCNT2) operates
independently (16TCNT2 presetting/clearing is
independent of other channels)
Channel 2 operates synchronously
Synchronous presetting/synchronous clearing
of 16TCNT2 is possible
H'FFF61
4 3
— — SYNC2
1 1
— —
Channel 0 timer counter (16TCNT0) operates
independently (16TCNT0 presetting/clearing is
independent of other channels)
Channel 0 operates synchronously
Synchronous presetting/synchronous clearing
of 16TCNT0 is possible
(Initial value)
16-bit timer (all channels)
2 1
SYNC1 SYNC0
0 0
R/W R/W R/W
(Initial value)
(Initial value)
0
0