Hitachi H8/3062 Hardware Manual page 849

16TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
Clock edge 1 and 0
Bit 4
CKEG
0
0
1
Counter clear 1 and 0
Bit 6 Bit 5
CCLR1 CCLR0
0
0
1
0
1
1
834
7 6 5
—
CCLR1 CCLR0
1 0 0
— R/W R/W
Timer prescaler 2 to 0
Bit 2 Bit 1
TPSC2 TPSC1
0
0
1
0
1
1
Bit 3
CKEG0
0 Rising edges counted
1 Falling edges counted
—
Both edges counted
16TCNT is not cleared
16TCNT is cleared by GRA compare match or input capture
16TCNT is cleared by GRB compare match or input capture
Synchronous clear : 16TCNT is cleared in synchronization with
other synchronized timers
H'FFF68
4 3
CKEG1 CKEG0
0 0
R/W R/W
Bit 0
TPSC0
0
Internal clock : ø
1
Internal clock : ø / 2
0
Internal clock : ø / 4
1 Internal clock : ø / 8
0 External clock A : TCLKA input
1
External clock B : TCLKB input
0
External clock C : TCLKC input
1
External clock D : TCLKD input
Description
Description
16-bit timer channel 0
2 1
TPSC2 TPSC1 TPSC0
0 0
R/W R/W R/W
Description
(Initial value)
(Initial value)
0
0
(Initial value)