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5.4.3
Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5
Interrupt Response Time
No.
Item
1
Interrupt priority
decision
2
Maximum number
of states until end of
current instruction
3
Saving PC and CCR
to stack
4
Vector fetch
5
Instruction fetch*
6
Internal processing*
Total
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after vector
fetch.
4. The number of states increases if wait states are inserted in external memory access.
On-Chip
Memory
1
2*
1 to 23
4
4
2
4
3
4
19 to 41
External Memory
8-Bit Bus
2 States
3 States
1
1
2*
2*
1 to 27
1 to 31*
4
8
12*
4
8
12*
4
8
12*
4
4
31 to 57
43 to 73
16-Bit Bus
2 States
1
2*
4
1 to 23
4
4
4
4
19 to 41
3 States
1
2*
4
1 to 25*
4
6*
4
6*
4
6*
4
25 to 49
117
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