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10.2.5
Timer Control/Status Registers (8TCSR)
8TCSR0
Bit
Initial value
Read/Write
R/(W)*
8TCSR2
Bit
Initial value
Read/Write
R/(W)*
8TCSR1, 8TCSR3
Bit
Initial value
Read/Write
R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers (8TCSR) are 8-bit registers that indicate compare match/input
capture and timer overflow statuses, and control compare match output/input capture edge
selection.
Each 8TCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the
occurrence of a TCORB compare match or input capture.
Bit 7
CMFB
Description
0
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
1
[Setting conditions]
•
•
7
6
CMFB
CMFA
OVF
0
0
R/(W)*
R/(W)*
7
6
CMFB
CMFA
OVF
0
0
R/(W)*
R/(W)*
7
6
CMFB
CMFA
OVF
0
0
R/(W)*
R/(W)*
8TCNT = TCORB
The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register
5
4
3
ADTE
OIS3
0
0
0
R/W
R/W
5
4
3
—
OIS3
0
1
0
—
R/W
5
4
3
ICE
OIS3
0
0
0
R/W
R/W
2
1
OIS2
OS1
OS0
0
0
R/W
R/W
R/W
2
1
OIS2
OS1
OS0
0
0
R/W
R/W
R/W
2
1
OIS2
OS1
OS0
0
0
R/W
R/W
R/W
(Initial value)
0
0
0
0
0
0
357
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