Serial Control Register (Scr) - Hitachi H8/3062 Hardware Manual

Bit 7
GM Description
0 Normal smart card interface mode operation
•
The TEND flag is set 12.5 etu after the beginning of the start bit.
•
Clock output on/off control only.
1 GSM mode smart card interface mode operation
•
The TEND flag is set 11.0 etu after the beginning of the start bit.
•
Clock output on/off and fixed-high/fixed-low control.
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 12.2.5,
Serial Mode Register (SMR).
13.2.4

Serial Control Register (SCR)

The function of SCR bits 1 and 0 is modified in smart card interface mode.
Bit
TIE
Initial value
Read/Write
R/W
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 12.2.6,
Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7 Bit 1
GM CKE1
0 0
1
1
424
7 6
RIE TE
0 0
R/W R/W
Bit 0
CKE0 Description
0 Internal clock/SCK pin is I/O port
1 Internal clock/SCK pin is clock output
0 Internal clock/SCK pin is fixed at low output
1 Internal clock/SCK pin is clock output
0 Internal clock/SCK pin is fixed at high output
1 Internal clock/SCK pin is clock output
5 4
RE MPIE
0 0
R/W R/W
3 2
TEIE CKE1
0 0
R/W R/W
(Initial value)
1 0
CKE0
0 0
R/W
(Initial value)