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8TCR2—Timer Control Register 2
8TCR3—Timer Control Register 3
7
Bit
CMIEB
Initial value
0
Read/Write
R/W
Compare match interrupt enable B
0
1
6
5
CMIEA
OVIE
CCLR1
0
0
R/W
R/W
Counter clear 1 and 0
0
1
Timer overflow interrupt enable
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
H'FFF90
H'FFF91
4
3
2
CCLR0
CKS2
0
0
0
R/W
R/W
R/W
Clock select 2 to 0
CSK2 CSK1 CSK0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
Note: * If the clock input of channel 2 is the 8TCNT3 overflow
signal and that of channel 3 is the 8TCNT2 compare
match signal, no incrementing clock is generated. Do
not use this setting.
Clearing is disabled
0
1
Cleared by compare match A
0
Cleared by compare match B/input capture B
1
Cleared by input capture B
8-bit timer channel 2
8-bit timer channel 3
1
0
CKS1
CKS0
0
0
R/W
R/W
Description
Clock input is disabled
Internal clock: counted on rising edge
of φ/8
Internal clock: counted on rising edge
of φ/64
Internal clock: counted on rising edge
of φ/8192
Channel 2:
Count on 8TCNT3 overflow signal*
Channel 3:
Count on 8TCNT2 compare match A*
External clock: counted on falling edge
External clock: counted on rising edge
External clock: counted on both
rising and falling edges
847
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