Hitachi H8/3062 Hardware Manual page 170

Address bus
CS
AS
RD
D
Read access
15
D to D
7
HWR
LWR
Write access
D
15
D to D
7
Note: n = 7 to 0
Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
T
1
φ
n
to D
8
0
to D
8
0
(Word Access)
Bus cycle
T
2
External address in area n
Valid
Valid
T
3
Valid
Valid
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