Upper-byte read
CPU
Bus interface
(H'AA)
Lower-byte read
CPU
Bus interface
(H'40)
Figure 14.2 A/D Data Register Access Operation (Reading H'AA40)
ADDRnH
(H'AA)
ADDRnH
(H'AA)
Module data bus
TEMP
(H'40)
ADDRnL
(H'40)
(n = A to D)
Module data bus
TEMP
(H'40)
ADDRnL
(H'40)
(n = A to D)
451