Bit Rate Register (Brr) - Hitachi H8/3062 Hardware Manual

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Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format in selected for transmitting in asynchronous mode.
The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not
selected, or when the SCI cannot transmit.
Bit 0
MPBT
0
1
12.2.8

Bit Rate Register (BRR)

BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS0 and CKS1 in SMR.
7
Bit
1
Initial value
Read/Write
R/W
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in standby mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 12.3 shows examples of BRR settings in asynchronous mode. Table 12.4 shows examples
of BRR settings in synchronous mode.
376
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
6
1
R/W
R/W
5
4
1
1
R/W
3
2
1
1
R/W
R/W
(Initial value)
1
0
1
1
R/W
R/W

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