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Table 8.7 (c) 16-bit timer Operating Modes (Channel 2)
Operating Mode
Synchronous preset
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
Phase counting
mode
Legend:
Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
TSNC
Synchro-
nization
MDF
FDIR PWM
SYNC2 = 1
—
—
—
—
—
—
—
—
SYNC2 = 1
—
MDF = 1
Register Settings
TMDR
IOA
PWM2 = 1
—
PWM2 = 0
IOA2 = 0
Other bits
unrestricted
PWM2 = 0
IOA2 = 1
Other bits
unrestricted
PWM2 = 0
TIOR2
16TCR2
Clear
IOB
Select
*
IOB2 = 0
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
Clock
Select
—
279
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