Table of Contents
Advertisement
To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in
accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied,
and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog
timer or other means. There may also be cases where the flash memory is in an erroneous
programming or erroneous erasing state at the point of transition to this protection mode, or where
programming or erasing is not properly carried out because of an abort. In cases such as these, a
forced recovery (program rewrite) must be executed using boot mode. However, it may also
happen that boot mode cannot be normally initiated because of overprogramming or overerasing.
17.6.4
NMI Input Disabling Conditions
NMI input is disabled when flash memory is being programmed or erased and while the boot
program is executing in boot mode (until a branch is made to the on-chip RAM area)*
priority to the program or erase operation. There are three reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
be read correctly*
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests (exception handling and bus release),
including NMI, must therefore be restricted inside and outside the MCU during FWE application.
NMI input is also disabled in the error protection state and while the P or E bit remains set in
FLMCR during flash memory emulation in RAM.
Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM
H'FFEF20 to H'FFF3FF (This branch takes place immediately after transfer of the user
program is completed). Consequently, after the branch to the RAM area, NMI input is
enabled except during programming and erasing. Interrupt requests must therefore be
disabled inside and outside the MCU until the user program has completed initial
programming (including the vector table and the NMI interrupt handling routine).
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased, correct read data will
not be obtained (undetermined values will be returned).
• If the NMI entry in the vector table has not been programmed yet, NMI exception
handling will not be executed correctly.
506
2
, possibly resulting in MCU runaway.
1
, to give
Advertisement
Table of Contents
