Table of Contents
Advertisement
Contention between General Register Write and Compare Match: If a compare match occurs
in the T
state of a general register write cycle, writing takes priority and the compare match signal
3
is inhibited. See figure 8.40.
φ
Address bus
Internal write signal
16TCNT
GR
Compare match signal
Figure 8.40 Contention between General Register Write and Compare Match
General register write cycle
T
T
1
2
GR address
N
N
General register write data
T
3
N + 1
M
Inhibited
271
Advertisement
Table of Contents
