Hitachi H8/3062 Hardware Manual page 510

Single-chip microcomputer
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since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by setting pins MD
setting conditions shown in table 17.6, and then executing a reset-start.
On reset release (a low-to-high transition)*
internally and maintains the boot mode state. Boot mode can be cleared by driving the FWE
pin low, then executing reset release*
a. When switching from boot mode to normal mode, the boot mode state within the chip must
first be cleared by reset input via the RES pin. The RES pin must be held low for at least 20
system clock cycles.*
b. Do not change the input levels at the mode pins (MD
boot mode. When making a mode transition, first enter the reset state by inputting a low
level to the RES pin. If a watchdog timer reset occurs in the boot mode state, the MCU's
internal state will not be cleared, and the on-chip boot program will be restarted regardless
of the mode pin settings.
c. The FWE pin must not be driven low while the boot program is running or flash memory is
being programmed or erased*
7. If the mode pin and FWE pin input levels are changed from 0 V to V
during a reset (while a low level is being input to the RES pin), the microcomputer's operating
mode will change. As a result, the state of ports with multiplexed address functions and bus
control output pins (CSn, AS, RD, HWR, LWR) will also change. Therefore, care must be
taken to make pin settings to prevent these pins from being used directly as output signal pins
during a reset, or to prevent collision with signals outside the MCU.
H8/3062F-ZTAT or
H8/3062F-ZTAT
R-mask version
1
, the MCU latches the current mode pin states
1
, but the following points must be noted.
3
2
.
CSn
MD2
MD1
MD0
FWE
RES
to MD
and FWE in accordance with the mode
0
2
to MD
) or the FWE pin while in
2
0
System
control
unit
or from V
to 0 V
CC
CC
External
memory,
etc.
493

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