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22.5.2
Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 22.14 shows the reset input timing.
• Reset output timing*
Figure 22.15 shows the reset output timing.
• Interrupt input timing
Figure 22.16 shows the interrupt input timing for NMI and IRQ
φ
RES
FWE
MD
to MD
2
0
φ
RESO
Note: * This function is used only in mask ROM models, and is not provided in flash memory
models.
t
RESS
t
MDS
Figure 22.14 Reset Input Timing
t
RESD
Figure 22.15 Reset Output Timing*
to IRQ
.
5
0
t
RESS
t
RESW
t
RESD
t
RESOW
733
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