Table of Contents
Advertisement
19.3.3
Erase Block Register (EBR)
EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode or software standby mode, when a high level is not
input to the FWE pin, or when the SWE bit in FLMCR1 is 0 when a high level is applied to the
FWE pin. When a bit is set in EBR, the corresponding block can be erased. Other blocks are erase-
protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not set bits
in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR1 is set. The flash memory block
configuration is shown in table 19.5. To erase all the blocks, erase each block sequentially.
The H8/3062F-ZTAT A-mask version does not support the on-board programming mode in mode
6, so bits in this register cannot be set to 1 in mode 6.
Bit
Initial value
Modes 1
Read/Write
to 4, and 6
Modes 5
Initial value
and 7
Read/Write
Bits 7 to 0—Block 7 to Block 0 (EB7 to EB0): Setting one of these bits specifies the
corresponding block (EB7 to EB0) for erasure.
Bits 7–0
EB7–EB0
Description
0
Corresponding block (EB7 to EB0) not selected
1
Corresponding block (EB7 to EB0) selected
Note: When not performing an erase, clear all EBR bits to 0.
578
7
6
EB7
EB6
EB5
0
0
R
R
0
0
R/W
R/W
R/W
5
4
3
EB4
EB3
0
0
0
R
R
R
0
0
0
R/W
R/W
2
1
EB2
EB1
EB0
0
0
R
R
0
0
R/W
R/W
R/W
(Initial value)
0
0
R
0
Advertisement
Table of Contents
