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Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS
in the high-impedance state in software standby mode.
Bit 1
SSOE
Description
0
In software standby mode, the address bus and bus control signals are all high-
impedance
1
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
3.4
Operating Mode Descriptions
3.4.1
Mode 1
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2
Mode 2
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
to CS
, AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed
0
7
to A
, permitting access to a maximum 1-Mbyte
19
0
to A
, permitting access to a maximum 1-Mbyte
19
0
(Initial value)
(Initial value)
(Initial value)
69
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