Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0
compare match or input capture events.
Bit 0
IMFA0
Description
0
[Clearing condition]
Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag
1
[Setting conditions]
•
16TCNT0 = GRA0 when GRA0 functions as an output compare register
•
16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0
functions as an input capture register
8.2.5
Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables GRB compare match and input capture interrupt requests.
Bit
7
—
Initial value
1
Read/Write
—
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode.
6
5
IMIEB2
IMIEB1
IMIEB0
0
0
R/W
R/W
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
4
3
—
IMFB2
0
1
R/W
—
R/(W)*
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
Reserved bit
2
1
0
IMFB1
IMFB0
0
0
0
R/(W)*
R/(W)*
(Initial value)
231