Hitachi H8/3062 Hardware Manual page 887

ADDRC H/L—A/D Data Register C H/L
Bit
Initial value
Read/Write
ADDRD H/L—A/D Data Register D H/L
Bit
Initial value
Read/Write
ADCR—A/D Control Register
Bit
Initial value
Read/Write
872
15 14 13 12 11
AD9 AD8 AD7 AD6 AD5
0 0 0 0 0
R R R R R
ADDRCH
A/D conversion data
10-bit data giving an A/D conversion result
15 14 13 12 11
AD9 AD8 AD7 AD6 AD5
0 0 0 0 0
R R R R R
ADDRDH
A/D conversion data
10-bit data giving an A/D conversion result
7 6
TRGE
0 1
R/W
Trigger Enable
A/D conversion start by external trigger or 8-bit timer
0
compare match is disabled
A/D conversion is started by falling edge of external
1
trigger signal (ADTRG) or 8-bit timer compare match
10 9 8 7 6
AD4 AD3 AD2 AD1 AD0
0 0 0 0 0
R R R R R
10 9 8 7 6
AD4 AD3 AD2 AD1 AD0
0 0 0 0 0
R R R R R
5 4 3
1 1 1
H'FFFE4, H'FFFE5
5 4 3 2 1
0 0 0 0 0
R R R R R
ADDRCL
H'FFFE6, H'FFFE7
5 4 3 2 1
0 0 0 0 0
R R R R R
ADDRDL
H'FFFE9
2 1
1 1
R/W
A/D
0
0
R
A/D
0
0
R
A/D
0
0