Register Descriptions - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer
Hide thumbs Also See for H8/3062:
Table of Contents

Advertisement

7.12.2

Register Descriptions

Table 7.22 summarizes the registers of port B.
Table 7.22 Port B Registers
Address*
Name
H'EE00A
Port B data direction register
H'FFFDA
Port B data register
Note: * Lower 20 bits of the address in advanced mode.
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
PB DDR
Initial value
Read/Write
The pin functions that can be selected for port B differ between modes 1 to 5, and modes 6 and 7.
For the method of selecting the pin functions, see tables 7.23 and 7.24.
When port B functions as an input/output port, a pin in port B becomes an output port if the
corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin
maintains its output state.
210
7
6
PB DDR
PB DDR
7
6
0
0
W
W
Abbreviation
PBDDR
PBDR
5
4
PB DDR
PB DDR
5
4
0
0
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
R/W
Initial Value
W
H'00
R/W
H'00
3
2
PB DDR
PB DDR
3
2
0
0
W
W
1
0
PB DDR
1
0
0
0
W
W

Advertisement

Table of Contents
loading

Table of Contents