Section 11 Watchdog Timer; Overview; Features - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer

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The H8/3062 Series has an on-chip watchdog timer (WDT). The WDT has two selectable

functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an

interval timer. As a watchdog timer, it generates a reset signal for the H8/3062 chip if a system

crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer

operation, an interval timer interrupt is requested at each TCNT overflow.

WDT features are listed below.

• Selection of eight counter clock sources

φ/2, φ /32, φ /64, φ /128, φ /256, φ /512, φ /2048, or φ /4096

• Interval timer option

• Timer counter overflow generates a reset signal or interrupt.

The reset signal is generated in watchdog timer operation. An interval timer interrupt is

generated in interval timer operation.

• Watchdog timer reset signal resets the entire H8/3062 internally, and can also be output

The reset signal generated by timer counter overflow during watchdog timer operation resets

the entire H8/3062 internally. An external reset signal can be output from the RESO pin to

reset other system devices simultaneously. In the versions with on-chip flash memory, the

RESO pin functions as the FWE pin, and therefore there is no function for outputting a reset

signal externally.

Section 11 Watchdog Timer