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SYSCR—System Control Register
7
Bit
SSBY
Initial value
0
Read/Write
R/W
Standby timer select 2 to 0
Bit 6
STS2
Software standby
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
806
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
User bit enable
0
1
Bit 5
Bit 4
STS1
STS0
Waiting Time = 8,192 states
0
0
1
Waiting Time = 16,384 states
0
Waiting Time = 32,768 states
0
1
Waiting Time = 65,536 states
1
0
Waiting Time = 131,072 states
0
Waiting Time = 26,2144 states
1
1
0
Waiting Time = 1,024 states
1
Illegal setting
1
3
2
UE
NMIEG
1
0
R/W
R/W
NMI edge select
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
CCR bit 6 (UI) is used as an interrupt mask bit
CCR bit 6 (UI) is used as a user bit
Standby Timer
H'EE012
System control
1
0
SSOE
RAME
0
1
R/W
R/W
RAM enable
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Software standby output port enable
In software standby mode,
all address bus and bus
0
control signals are high-
impedance
In software standby mode,
address bus retains output
state and bus control
1
signals are fixed high
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